Subject:CODL
UNIT-III
1. Latches constructed with NOR and NAND gates tend to remain in the latched condition
due to which configuration feature?
a) Low input voltages
b) Synchronous operation
c) Gate impedance
d) Cross coupling
Answer: d
Explanation: Latch is a type of bistable multivibrator having two stable states. Both inputs
of a latch are directly connected to the other’s output. Such types of structure is called
cross coupling and due to which latches remain in the latched condition.
2. One example of the use of an S-R flip-flop is as ___________
a) Transition pulse generator
b) Racer
c) Switch debouncer
d) Astable oscillator
Answer: c
Explanation: The SR flip-flop is very effective in removing the effects of switch bounce,
which is the unwanted noise caused during the switching of electronic devices.
3. The truth table for an S-R flip-flop has how many VALID entries?
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: The SR flip-flop actually has three inputs, Set, Reset and its current state.
The Invalid or Undefined State occurs at both S and R being at 1.
4. When both inputs of a J-K flip-flop cycle, the output will ___________
a) Be invalid
b) Change
c) Not change
d) Toggle
Answer: c
Explanation: After one cycle the value of each input comes to the same value. Eg: Assume
J=0 and K=1. After 1 cycle, it becomes as J=0->1->0(1 cycle complete) and K=1->0->1(1
cycle complete). The J & K flip-flop has 4 stable states: Latch, Reset, Set and Toggle.
5. Which of the following is correct for a gated D-type flip-flop?
a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGH
Answer: a
Explanation: In D flip flop, when the clock is high then the output depends on the input
otherwise reminds previous output. In a state of clock high, when D is high the output Q
also high, if D is ‘0’ then output is also zero. Like SR flip-flop, the D-flip-flop also have an
invalid state at both inputs being 1.
6. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates
Answer: c
Explanation: The basic S-R flip-flop can be constructed by cross coupling of NOR or
NAND gates. Cross coupling means the output of second gate is fed to the input of first
gate and vice-versa.
7. The logic circuits whose outputs at any instant of time depends only on the present input
but also on the past outputs are called ________________
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
Answer: b
Explanation: In sequential circuits, the output signals are fed back to the input side. So,
The circuits whose outputs at any instant of time depends only on the present input but
also on the past outputs are called sequential circuits. Unlike sequential circuits, if output
depends only on the present state, then it’s known as combinational circuits.
8. Whose operations are more faster among the following?
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
Answer: a
Explanation: Combinational circuits are often faster than sequential circuits. Since the
combinational circuits do not require memory elements whereas the sequential circuits
need memory devices to perform their operations in sequence. Latches and Flip-flops
come under sequential circuits.
9. How many types of sequential circuits are?
a) 2
b) 3
c) 4
d) 5
Answer: a
Explanation: There are two type of sequential circuits viz., (i) synchronous or clocked and
(ii) asynchronous or unclocked. Synchronous Sequential Circuits are triggered in the
presence of a clock signal, whereas, Asynchronous Sequential Circuits function in the
absence of a clock signal.
10. The sequential circuit is also called ___________
a) Flip-flop
b) Latch
c) Strobe
d) Adder
Answer: b
Explanation: The sequential circuit is also called a latch because both are a memory cell,
which are capable of storing one bit of information.
11. The basic latch consists of ___________
a) Two inverters
b) Two comparators
c) Two amplifiers
d) Two adders
Answer: a
Explanation: The basic latch consists of two inverters. It is in the sense that if the output Q
= 0 then the second output Q’ = 1 and vice versa.
12. In S-R flip-flop, if Q = 0 the output is said to be ___________
a) Set
b) Reset
c) Previous state
d) Current state
Answer: b
Explanation: In S-R flip-flop, if Q = 0 the output is said to be reset and set for Q = 1.
13. The output of latches will remain in set/reset untill ___________
a) The trigger pulse is given to change the state
b) Any pulse given to go into previous state
c) They don’t get any pulse more
d) The pulse is edge-triggered
Answer: a
Explanation: The output of latches will remain in set/reset untill the trigger pulse is given to
change the state.
14. What is a trigger pulse?
a) A pulse that starts a cycle of operation
b) A pulse that reverses the cycle of operation
c) A pulse that prevents a cycle of operation
d) A pulse that enhances a cycle of operation
Answer: a
Explanation: Trigger pulse is defined as a pulse that starts a cycle of operation.
15. The circuits of NOR based S-R latch classified as asynchronous sequential circuits,
why?
a) Because of inverted outputs
b) Because of triggering functionality
c) Because of cross-coupled connection
d) Because of inverted outputs & triggering functionality
Answer: c
Explanation: The cross-coupled connections from the output of one gate to the input of the
other gate constitute a feedback path. For this reason, the circuits of NOR based S-R latch
classified as asynchronous sequential circuits. Moreover, they are referred to as
asynchronous because they function in the absence of a clock pulse.
16. In digital logic, a counter is a device which ____________
a) Counts the number of outputs
b) Stores the number of times a particular event or process has occurred
c) Stores the number of times a clock pulse rises and falls
d) Counts the number of inputs
Answer: b
Explanation: In digital logic and computing, a counter is a device which stores (and
sometimes displays) the number of times a particular event or process has occurred, often
in relationship to a clock signal.
17. A counter circuit is usually constructed of ____________
a) A number of latches connected in cascade form
b) A number of NAND gates connected in cascade form
c) A number of flip-flops connected in cascade
d) A number of NOR gates connected in cascade form
Answer: c
Explanation: A counter circuit is usually constructed of a number of flip-flops connected in
cascade. Preferably, JK Flip-flops are used to construct counters and registers.
18. What is the maximum possible range of bit-count specifically in n-bit binary counter
consisting of ‘n’ number of flip-flops?
a) 0 to 2n
b) 0 to 2n + 1
c) 0 to 2n – 1
d) 0 to 2n+1/2
Answer: c
Explanation: The maximum possible range of bit-count specifically in n-bit binary counter
consisting of ‘n’ number of flip-flops is 0 to 2n-1. For say, there is a 2-bit counter, then it will
count till 22-1 = 3. Thus, it will count from 0 to 3.
19. How many types of the counter are there?
a) 2
b) 3
c) 4
d) 5
Answer: b
Explanation: Counters are of 3 types, namely, (i)asynchronous/synchronous, (ii)single and
multi-mode & (iii)modulus counter. These further can be subdivided into Ring Counter,
Johnson Counter, Cascade Counter, Up/Down Counter and such like.
20. A decimal counter has ______ states.
a) 5
b) 10
c) 15
d) 20
Answer: b
Explanation: Decimal counter is also known as 10 stage counter. So, it has 10 states. It is
also known as Decade Counter counting from 0 to 9.
21. Ripple counters are also called ____________
a) SSI counters
b) Asynchronous counters
c) Synchronous counters
d) VLSI counters
Answer: b
Explanation: Ripple counters are also called asynchronous counter. In Asynchronous
counters, only the first flip-flop is connected to an external clock while the rest of the
flip-flops have their preceding flip-flop output as clock to them.
22. Synchronous counter is a type of ____________
a) SSI counters
b) LSI counters
c) MSI counters
d) VLSI counters
Answer: c
Explanation: Synchronous Counter is a Medium Scale Integrated (MSI). In Synchronous
Counters, the clock pulse is supplied to all the flip-flops simultaneously.
23. Three decade counter would have ____________
a) 2 BCD counters
b) 3 BCD counters
c) 4 BCD counters
d) 5 BCD counters
Answer: b
Explanation: Three decade counter has 30 states and a BCD counter has 10 states. So, it
would require 3 BCD counters. Thus, a three decade counter will count from 0 to 29.
24. BCD counter is also known as ____________
a) Parallel counter
b) Decade counter
c) Synchronous counter
d) VLSI counter
Answer: b
Explanation: BCD counter is also known as decade counter because both have the same
number of stages and both count from 0 to 9.
25. The parallel outputs of a counter circuit represent the _____________
a) Parallel data word
b) Clock frequency
c) Counter modulus
d) Clock count
Answer: d
Explanation: The parallel outputs of a counter circuit represent the clock count. A counter
counts the number of times an event takes place in accordance to the clock pulse.
26. How many natural states will there be in a 4-bit ripple counter?
a) 4
b) 8
c) 16
d) 32
Answer: c
Explanation: In an n-bit counter, the total number of states = 2n.
Therefore, in a 4-bit counter, the total number of states = 24 = 16 states.
27. A ripple counter’s speed is limited by the propagation delay of _____________
a) Each flip-flop
b) All flip-flops and gates
c) The flip-flops only with gates
d) Only circuit gates
Answer: a
Explanation: A ripple counter is something that is derived by other flip-flops. It’s like a
series of Flip Flops. Output of one FF becomes the input of the next. Because ripple
counter is composed of FF only and no gates are there other than FF, so only propagation
delay of FF will be taken into account. Propagation delay refers to the amount of time
taken in producing an output when the input is altered.
28. One of the major drawbacks to the use of asynchronous counters is that
____________
a) Low-frequency applications are limited because of internal propagation delays
b) High-frequency applications are limited because of internal propagation delays
c) Asynchronous counters do not have major drawbacks and are suitable for use in high-
and low-frequency counting applications
d) Asynchronous counters do not have propagation delays, which limits their use in
high-frequency applications
Answer: b
Explanation: One of the major drawbacks to the use of asynchronous counters is that
High-frequency applications are limited because of internal propagation delays.
Propagation delay refers to the amount of time taken in producing an output when the
input is altered.
29. Internal propagation delay of asynchronous counter is removed by ____________
a) Ripple counter
b) Ring counter
c) Modulus counter
d) Synchronous counter
Answer: d
Explanation: Propagation delay refers to the amount of time taken in producing an output
when the input is altered. Internal propagation delay of asynchronous counter is removed
by synchronous counter because clock input is given to each flip-flop individually in
synchronous counter.
30. What happens to the parallel output word in an asynchronous binary down counter
whenever a clock pulse occurs?
a) The output increases by 1
b) The output decreases by 1
c) The output word increases by 2
d) The output word decreases by 2
Answer: b
Explanation: In an asynchronous counter, there isn’t any clock input. The output of 1st
flip-flop is given to second flip-flop as clock input. So, in case of binary down counter the
output word decreases by 1.
31. How many flip-flops are required to construct a decade counter?
a) 4
b) 8
c) 5
d) 10
Answer: a
Explanation: Number of flip-flop required is calculated by this formula: 2(n-1) <= N< = 2n.
24=16and23=8, therefore, 4 flip flops needed.
32. How many different states does a 3-bit asynchronous counter have?
a) 2
b) 4
c) 8
d) 16
Answer: c
Explanation: In a n-bit counter, the total number of states = 2n.
Therefore, in a 3-bit counter, the total number of states = 23 = 8 states.
33. A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns
propagation delay. The total propagation delay (tp(total)) is ____________
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
Answer: d
Explanation: Since a counter is constructed using flip-flops, therefore, the propagation
delay in the counter occurs only due to the flip-flops. Each bit has propagation delay =
12ns. So, 5 bits = 12ns * 5 = 60ns.
34. An asynchronous 4-bit binary down counter changes from count 2 to count 3. How
many transitional states are required?
a) 1
b) 2
c) 8
d) 15
Answer: d
Explanation: Transitional state is given by (2n – 1). Since, it’s a 4-bit counter, therefore,
transition states = 24 – 1 = 15. So, total transitional states are 15.
35. A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from
clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of
____________
a) 15 ns
b) 30 ns
c) 45 ns
d) 60 ns
Answer: d
Explanation: Since a counter is constructed using flip-flops, therefore, the propagation
delay in the counter occurs only due to the flip-flops. One bit change is 15 ns, so 4-bit
change = 15 * 4 = 60.
36. Three cascaded decade counters will divide the input frequency by ____________
a) 10
b) 20
c) 100
d) 1000
Answer: d
Explanation: Decade counter has 10 states. So, three decade counters are cascaded i.e.
10*10*10=1000 states.
37. A ripple counter’s speed is limited by the propagation delay of ____________
a) Each flip-flop
b) All flip-flops and gates
c) The flip-flops only with gates
d) Only circuit gates
Answer: a
Explanation: A ripple counter is something that is derived by other flip-flops. Its like a
series of Flip Flops. Output of one FF becomes the input of the next. Because ripple
counter is composed of FF only and no gates are there other than FF, so only propagation
delay of FF will be taken into account. Propagation delay refers to the amount of time
taken in producing an output when the input is altered.
38. A 4-bit counter has a maximum modulus of ____________
a) 3
b) 6
c) 8
d) 16
Answer: d
Explanation: In a n-bit counter, the total number of states = 2n.
Therefore, in a 4-bit counter, the total number of states = 24 = 16 states.
39. A principle regarding most display decoders is that when the correct input is present,
the related output will switch ____________
a) HIGH
b) To high impedance
c) To an open
d) LOW
Answer: d
Explanation: A principle regarding most display decoders is that when the correct input is
present, the related output will switch LOW. Since it’s an active-low device.
40.Which of the following statements are true?
a) Asynchronous events does not occur at the same time
b) Asynchronous events are controlled by a clock
c) Synchronous events does not need a clock to control them
d) Only asynchronous events need a control clock
Answer: a
Explanation: Asynchronous events does not occur at the same time because of
propagation delay and they do need a clock pulse to trigger them. Whereas, synchronous
events occur in presence of clock pulse.
41. A down counter using n-flip-flops count ______________
a) Downward from a maximum count
b) Upward from a minimum count
c) Downward from a minimum to maximum count
d) Toggles between Up and Down count
Answer: a
Explanation: As the name suggests down counter means counting occurs from a higher
value to lower value (i.e. (2^n – 1) to 0).
42. UP Counter is ____________
a) It counts in upward manner
b) It count in down ward manner
c) It counts in both the direction
d) Toggles between Up and Down count
Answer: a
Explanation: UP counter counts in an upward manner from 0 to (2n – 1).
43. DOWN counter is ____________
a) It counts in upward manner
b) It count in downward manner
c) It counts in both the direction
d) Toggles between Up and Down count
Answer: b
Explanation: DOWN counter counts in a downward manner from (2n – 1) to 0.
44.How many different states does a 3-bit asynchronous down counter have?
a) 2
b) 4
c) 6
d) 8
Answer: d
Explanation: In a n-bit counter, the total number of states = 2n.
Therefore, in a 3-bit counter, the total number of states = 23 = 8 states.
45.In a down counter, which flip-flop doesn’t toggle when the inverted output of the
preceeding flip-flop goes from HIGH to LOW.
a) MSB flip-flop
b) LSB flip-flop
c) Master slave flip-flop
d) Latch
Answer: b
Explanation: Since the LSB flip-flop changes its state at each negative transition of clock.
That is why LSB flip-flop doesn’t have toggle.
46. In a 3-bit asynchronous down counter, the initial content is ____________
a) 000
b) 111
c) 010
d) 101
Answer: a
Explanation: Initially, all the flip-flops are RESET. So, the initial content is 000. At the first
negative transition of the clock, the counter content becomes 101.
47. In a 3-bit asynchronous down counter, at the first negative transition of the clock, the
counter content becomes ____________
a) 000
b) 111
c) 101
d) 010
Answer: b
Explanation: Since, in the down counter, the counter content is decremented by 1 for every
negative transition. Hence, in a 3-bit asynchronous down counter, at the first negative
transition of the clock, the counter content becomes 111.
48. In a 3-bit asynchronous down counter, at the first negative transition of the clock, the
counter content becomes ____________
a) 000
b) 111
c) 101
d) 010
Answer: c
Explanation: Since, in the down counter, the counter content is decremented by 1 for every
negative transition. Hence, in a 3-bit asynchronous down counter, at the first negative
transition of the clock, the counter content becomes 101.
49. The hexadecimal equivalent of 15,536 is ________
a) 3CB0
b) 3C66
c) 63C0
d) 6300
Answer: a
Explanation: You just divide the number by 16 at the end and store the remainder from
bottom to top.
50. In order to check the CLR function of a counter ____________
a) Apply the active level to the CLR input and check all of the Q outputs to see if they are
all in their reset state
b) Ground the CLR input and check to be sure that all of the Q outputs are LOW
c) Connect the CLR input to Vcc and check to see if all of the Q outputs are HIGH
d) Connect the CLR to its correct active level while clocking the counter; check to make
sure that all of the Q outputs are toggling
Answer: a
Explanation: CLR stands for clearing or resetting all states of flip-flop. In order to check the
CLR function of a counter, apply the active level to the CLR input and check all of the Q
outputs to see if they are all in their reset state.
51.In digital logic, a counter is a device which ____________
a) Counts the number of outputs
b) Stores the number of times a particular event or process has occurred
c) Stores the number of times a clock pulse rises and falls
d) Counts the number of inputs
Answer: b
Explanation: In digital logic and computing, a counter is a device which stores (and
sometimes displays) the number of times a particular event or process has occurred, often
in relationship to a clock signal.
52. A counter circuit is usually constructed of ____________
a) A number of latches connected in cascade form
b) A number of NAND gates connected in cascade form
c) A number of flip-flops connected in cascade
d) A number of NOR gates connected in cascade form
Answer: c
Explanation: A counter circuit is usually constructed of a number of flip-flops connected in
cascade. Preferably, JK Flip-flops are used to construct counters and registers.
53. What is the maximum possible range of bit-count specifically in n-bit binary counter
consisting of ‘n’ number of flip-flops?
a) 0 to 2n
b) 0 to 2n + 1
c) 0 to 2n – 1
d) 0 to 2n+1/2
Answer: c
Explanation: The maximum possible range of bit-count specifically in n-bit binary counter
consisting of ‘n’ number of flip-flops is 0 to 2n-1. For say, there is a 2-bit counter, then it will
count till 22-1 = 3. Thus, it will count from 0 to 3.
54. How many types of the counter are there?
a) 2
b) 3
c) 4
d) 5
Answer: b
Explanation: Counters are of 3 types, namely, (i)asynchronous/synchronous, (ii)single and
multi-mode & (iii)modulus counter. These further can be subdivided into Ring Counter,
Johnson Counter, Cascade Counter, Up/Down Counter and such like.
55. A decimal counter has ______ states.
a) 5
b) 10
c) 15
d) 20
Answer: b
Explanation: Decimal counter is also known as 10 stage counter. So, it has 10 states. It is
also known as Decade Counter counting from 0 to 9.
56. Ripple counters are also called ____________
a) SSI counters
b) Asynchronous counters
c) Synchronous counters
d) VLSI counters
Answer: b
Explanation: Ripple counters are also called asynchronous counter. In Asynchronous
counters, only the first flip-flop is connected to an external clock while the rest of the
flip-flops have their preceding flip-flop output as clock to them.
57. Synchronous counter is a type of ____________
a) SSI counters
b) LSI counters
c) MSI counters
d) VLSI counters
Answer: c
Explanation: Synchronous Counter is a Medium Scale Integrated (MSI). In Synchronous
Counters, the clock pulse is supplied to all the flip-flops simultaneously.
58. Three decade counter would have ____________
a) 2 BCD counters
b) 3 BCD counters
c) 4 BCD counters
d) 5 BCD counters
Answer: b
Explanation: Three decade counter has 30 states and a BCD counter has 10 states. So, it
would require 3 BCD counters. Thus, a three decade counter will count from 0 to 29.
59. BCD counter is also known as ____________
a) Parallel counter
b) Decade counter
c) Synchronous counter
d) VLSI counter
Answer: b
Explanation: BCD counter is also known as decade counter because both have the same
number of stages and both count from 0 to 9.
60. Based on how binary information is entered or shifted out, shift registers are classified
into _______ categories.
a) 2
b) 3
c) 4
d) 5
Answer: c
Explanation: The registers in which data can be shifted serially or parallelly are known as
shift registers. Based on how binary information is entered or shifted out, shift registers are
classified into 4 categories, viz., Serial-In/Serial-Out(SISO), Serial-In/Parallel-Out (SIPO),
Parallel-In/Serial-Out (PISO), Parallel-In/Parallel-Out (PIPO).
61.The full form of SIPO is ___________
a) Serial-in Parallel-out
b) Parallel-in Serial-out
c) Serial-in Serial-out
d) Serial-In Peripheral-Out
Answer: a
Explanation: SIPO is always known as Serial-in Parallel-out.
62.A shift register that will accept a parallel input or a bidirectional serial load and internal
shift features is called as?
a) Tristate
b) End around
c) Universal
d) Conversion
Answer: c
Explanation: A shift register can shift it’s data either left or right. The universal shift register
is capable of shifting data left, right and parallel load capabilities.
63.How can parallel data be taken out of a shift register simultaneously?
a) Use the Q output of the first FF
b) Use the Q output of the last FF
c) Tie all of the Q outputs together
d) Use the Q output of each FF
Answer: d
Explanation: Because no other flip-flops are connected with the output Q, therefore one
can use the Q out of each FF to take out parallel data.
64.What is meant by the parallel load of a shift register?
a) All FFs are preset with data
b) Each FF is loaded with data, one at a time
c) Parallel shifting of data
d) All FFs are set with data
Answer: a
Explanation: At Preset condition, outputs of flip-flops will be 1. Preset = 1 means Q = 1,
thus input is definitely 1.
65.The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output
shift register with an initial state 01110. After three clock pulses, the register contains
________
a) 01110
b) 00001
c) 00101
d) 00110
Answer: c
Explanation: LSB bit is inverted and feed back to MSB:
01110->initial
10111->first clock pulse
01011->second
00101->third.
66.Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the
nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit
first)
a) 1100
b) 0011
c) 0000
d) 1111
Answer: c
Explanation: In Serial-In/Serial-Out shift register, data will be shifted one at a time with
every clock pulse. Therefore,
Wait | Store
1100 | 0000
110 | 0000 1st clock
11 | 0000 2nd clock.
67.A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is
waiting to enter. After four clock pulses, the register contains ________
a) 0000
b) 1111
c) 0111
d) 1000
Answer: c
Explanation: In Serial-In/Parallel-Out shift register, data will be shifted all at a time with
every clock pulse. Therefore,
Wait | Store
0111 | 0000
011 | 1000 1st clk
01 | 1100 2nd clk
0 | 1110 3rd clk
X | 1111 4th clk.
68.With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in
________
a) 4 μs
b) 40 μs
c) 400 μs
d) 40 ms
Answer: b
Explanation: f = 200 KHZ; T = (1/200) m sec = (1/0.2) micro-sec = 5 micro-sec;
In serial transmission, data enters one bit at a time. After 8 clock cycles only 8 bit will be
loaded = 8 * 5 = 40 micro-sec.
69.An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to
achieve a time delay (td) of ________
a) 16 us
b) 8 us
c) 4 us
d) 2 us
Answer: c
Explanation: One clock period is = (1⁄2) micro-s = 0.5 microseconds. In serial transmission,
data enters one bit at a time. So, the total delay = 0.5*8 = 4 micro seconds time is required
to transmit information of 8 bits.
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