Logic Design and Computer Organization UNIT-II

UNIT-II

1. In parts of the processor, adders are used to calculate ____________
a) Addresses
b) Table indices
c) Increment and decrement operators
d) All of the Mentioned
Answer: d
Explanation: Adders are used to perform the operation of addition. Thus, in parts of the processor, adders are used to calculate addresses, table indices, increment and decrement operators, and similar operations.

2. Total number of inputs in a half adder is __________
a) 2
b) 3
c) 4
d) 1
Answer: a
Explanation: Total number of inputs in a half adder is two. Since an EXOR gates has 2 inputs and carry is connected with the input of EXOR gates. The output of half-adder is also 2, them being, SUM and CARRY. The output of EXOR gives SUM and that of AND gives carry.

3. In which operation carry is obtained?
a) Subtraction
b) Addition
c) Multiplication
d) Both addition and subtraction
Answer: b
Explanation: In addition, carry is obtained. For example: 1 0 1 + 1 1 1 = 1 0 0; in this example carry is obtained after 1st addition (i.e. 1 + 1 = 1 0). In subtraction, borrow is obtained. Like, 0 – 1 = 1 (borrow 1).

4. If A and B are the inputs of a half adder, the sum is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
Answer: c
Explanation: If A and B are the inputs of a half adder, the sum is given by A XOR B, while the carry is given by A AND B.

5. If A and B are the inputs of a half adder, the carry is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
Answer: a
Explanation: If A and B are the inputs of a half adder, the carry is given by: A(AND)B, while the sum is given by A XOR B.

6. Half-adders have a major limitation in that they cannot __________
a) Accept a carry bit from a present stage
b) Accept a carry bit from a next stage
c) Accept a carry bit from a previous stage
d) Accept a carry bit from the following stages
Answer: c
Explanation: Half-adders have a major limitation in that they cannot accept a carry bit from a previous stage, meaning that they cannot be chained together to add multi-bit numbers. However, the two output bits of a half-adder can also represent the result A+B=3 as sum and carry both being high.

7. The difference between half adder and full adder is __________
a) Half adder has two inputs while full adder has four inputs
b) Half adder has one output while full adder has two outputs
c) Half adder has two inputs while full adder has three inputs
d) All of the Mentioned
Answer: c
Explanation: Half adder has two inputs while full adder has three outputs; this is the difference between them, while both have two outputs SUM and CARRY.

8. If A, B and C are the inputs of a full adder then the sum is given by __________
a) A AND B AND C
b) A OR B AND C
c) A XOR B XOR C
d) A OR B OR C
Answer: c
Explanation: If A, B and C are the inputs of a full adder then the sum is given by A XOR B XOR C.

9. If A, B and C are the inputs of a full adder then the carry is given by __________
a) A AND B OR (A OR B) AND C
b) A OR B OR (A AND B) C
c) (A AND B) OR (A AND B)C
d) A XOR B XOR (A XOR B) AND C
Answer: a
Explanation: If A, B and C are the inputs of a full adder then the carry is given by A AND B OR (A OR B) AND C, which is equivalent to (A AND B) OR (B AND C) OR (C AND A).

10. How many AND, OR and EXOR gates are required for the configuration of full adder?
a) 1, 2, 2
b) 2, 1, 2
c) 3, 1, 2
d) 4, 0, 1
Answer: b
Explanation: There are 2 AND, 1 OR and 2 EXOR gates required for the configuration of full adder, provided using half adder. Otherwise, configuration of full adder would require 3 AND, 2 OR and 2 EXOR.

11. What is the major difference between half-adders and full-adders?
a) Full-adders are made up of two half-adders
b) Full adders can handle double-digit numbers
c) Full adders have a carry input capability
d) Half adders can handle only single-digit numbers
Answer: c
Explanation: Half adders have only two inputs A and B. When we add two 4 bit binary number like 0001 and 0011, then half adder can not be used because if the first bit of both the numbers is 1, then the sum would be 0 and carry would be 1. But this carry can not be added with the second bits addition of the number. So, half adders are useless. But in full adders, one more carry input is present, so that, if carry of one stage is present, it can be added with the next stage as it is done in normal addition. So, therefore, full adders have a carry input capability.

12. The binary subtraction of 0 – 0 =?
a) Difference = 0, borrow = 0
b) Difference = 1, borrow = 0
c) Difference = 1, borrow = 1
d) Difference = 0, borrow = 1
Answer: a
Explanation: The binary subtraction of 0 – 0 = 0. Thus, it’s difference is 0 as well as it’s borrow. 

13. How many basic binary subtraction operations are possible?
a) 1
b) 4
c) 3
d) 2
Answer: b
Explanation: 4 basic binary subtraction operations (0-0, 1-0, 0-1, 1-1) are possible.
0 – 0 = 0
0 – 1 = 1 ( Borrow 1)
1 – 0 = 1
1 – 1 = 0

14. When performing subtraction by addition in the 2’s-complement system ____________
a) The minuend and the subtrahend are both changed to the 2’s-complement
b) The minuend is changed to 2’s-complement and the subtrahend is left in its original form
c) The minuend is left in its original form and the subtrahend is changed to its 2’s-complement
d) The minuend and subtrahend are both left in their original form
Answer: c
Explanation: When performing subtraction by addition in the 2’s-complement system, the minuend is left in its original form and the subtrahend is changed to its 2’s-complement. It is then added to the minuend. If the result has carry, then it’s dropped and that’s the final answer. Else, if the result has no carry, then the result is again converted to it’s 2’s complement form and that’s the final answer with a ‘negative’ sign.

15. What are the two types of basic adder circuits?
a) Sum and carry
b) Half-adder and full-adder
c) Asynchronous and synchronous
d) One and two’s-complement
Answer: b
Explanation: There are two types of adder circuits: half-adder and full-adder. Half-Adder has 2 inputs while Full-Adder has 3 inputs. Whereas, both have two outputs SUM and CARRY.

16. Which of the following is correct for full adders?
a) Full adders have the capability of directly adding decimal numbers
b) Full adders are used to make half adders
c) Full adders are limited to two inputs since there are only two binary digits
d) In a parallel full adder, the first stage may be a half adder
Answer: d
Explanation: By using maximum of two half adders we can make a full adder for the first stage of a Parallel Full adder. 

17. Half subtractor is used to perform subtraction of ___________
a) 2 bits
b) 3 bits
c) 4 bits
d) 5 bits
Answer: a
Explanation: Half subtractor is a combinational circuit which is used to perform subtraction of two bits, namely minuend and subtrahend and produces two outputs, borrow and difference.

18. For subtracting 1 from 0, we use to take a _______ from neighbouring bits.
a) Carry
b) Borrow
c) Input
d) Output
Answer: b
Explanation: For subtracting 1 from 0, we use to take a borrow from neighbouring bits because carry is taken into consideration during addition process.

19. How many outputs are required for the implementation of a subtractor?
a) 1
b) 2
c) 3
d) 4
Answer: b
Explanation: There are two outputs required for the implementation of a subtractor. One for the difference and another for borrow.

20. Let the input of a subtractor is A and B then what the output will be if A = B?
a) 0
b) 1
c) A
d) B
Answer: a
Explanation: The output for A = B will be 0. If A = B, it means that A = B = 0 or A = B = 1. In both of the situation subtractor gives 0 as the output.

21. Let A and B is the input of a subtractor then the output will be ___________
a) A XOR B
b) A AND B
c) A OR B
d) A EXNOR B
Answer: a
Explanation: The subtractor has two outputs BORROW and DIFFERENCE. Since the difference output of a subtractor is given by AB’ + BA’ and this is the output of a XOR gate. So, the final difference output is AB’ + BA’.

22. Let A and B is the input of a subtractor then the borrow will be ___________
a) A AND B’
b) A’ AND B
c) A OR B
d) A AND B
Answer: b
Explanation: The borrow of a subtractor is received through AND gate whose one input is inverted. On that basis the borrow will be (A’ AND B).

23. What does minuend and subtrahend denotes in a subtractor?
a) Their corresponding bits of input
b) Its outputs
c) Its inputs
d) Borrow bits
Answer: c
Explanation: Minuend and subtrahend are the two bits of input of a subtractor. If A and B are the two inputs of a subtractor then A is called minuend and B as subtrahend.

24. Full subtractor is used to perform subtraction of ___________
a) 2 bits
b) 3 bits
c) 4 bits
d) 8 bits
Answer: b
Explanation: Full subtractor is used to perform subtraction of 3 bits, namely minuend bit, subtrahend bit and borrow from the previous stage. However, it also produces 2 outputs BORROW and DIFFERENCE.

25. The full subtractor can be implemented using ___________
a) Two XOR and an OR gates
b) Two half subtractors and an OR gate
c) Two multiplexers and an AND gate
d) Two comparators and an AND gate

Answer: b
Explanation: A full subtractor has 3 input bits and two outputs bits BORROW and DIFFERENCE. The full subtractor can be implemented using two half subtractors and an OR gate.

26. The output of a subtractor is given by (if A, B and X are the inputs).
a) A AND B XOR X
b) A XOR B XOR X
c) A OR B NOR X
d) A NOR B XOR X
Answer: b
Explanation: The difference output of a subtractor is given by (if A, B and X are the inputs) A XOR B XOR X.

27. The output of a full subtractor is same as ____________
a) Half adder
b) Full adder
c) Half subtractor
d) Decoder
Answer: b
Explanation: The sum and difference output of a full adder and a full subtractor are same. If A, B and C are the input of a full adder and a full subtractor then the output will be given by (A XOR B XOR C), respectively.

28. What is a multiplexer?
a) It is a type of decoder which decodes several inputs and gives one output
b) A multiplexer is a device which converts many signals into one
c) It takes one input and results into many output
d) It is a type of encoder which decodes several inputs and gives one output
Answer: b
Explanation: A multiplexer (or MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line, depending on the active select lines.

29. Which combinational circuit is renowned for selecting a single input from multiple inputs & directing the binary information to output line?
a) Data Selector
b) Data distributor
c) Both data selector and data distributor
d) DeMultiplexer
Answer: a
Explanation: Data Selector is another name of Multiplexer. A multiplexer (or MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line, depending on the active select lines.

30. It is possible for an enable or strobe input to undergo an expansion of two or more MUX ICs to the digital multiplexer with the proficiency of large number of ___________
a) Inputs
b) Outputs
c) Selection lines
d) Enable lines
Answer: a
Explanation: It is possible for an enable or strobe input to undergo an expansion of two or more MUX ICs to the digital multiplexer with the proficiency of large number of inputs.

31. Which is the major functioning responsibility of the multiplexing combinational circuit?
a) Decoding the binary information
b) Generation of all minterms in an output function with OR-gate
c) Generation of selected path between multiple sources and a single destination
d) Encoding of binary information
Answer: c
Explanation: The major functioning responsibility of the multiplexing combinational circuit is generation of selected path between multiple sources and a single destination because it makes the circuit too flexible. A multiplexer (or MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line, depending on the active select lines.

32. What is the function of an enable input on a multiplexer chip?
a) To apply Vcc
b) To connect ground
c) To active the entire chip
d) To active one half of the chip
Answer: c
Explanation: Enable input is used to active the chip, when enable is high the chip works (ACTIVE), when enable is low the chip does not work (MEMORY). However, Enable can be Active-High or Active-Low, indicating it is active either when it is connected to VCC or GND respectively.

33. One multiplexer can take the place of ___________
a) Several SSI logic gates
b) Combinational logic circuits
c) Several Ex-NOR gates
d) Several SSI logic gates or combinational logic circuits
Answer: d
Explanation: A multiplexer (or MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line, depending on the active select lines. Since many operational behaviour can be performed by using a multiplexer. Whereas, a combinational circuit is a combination of many logic gates which makes the circuit more complex.

34. In a multiplexer, the selection of a particular input line is controlled by ___________
a) Data controller
b) Selected lines
c) Logic gates
d) Both data controller and selected lines
Answer: b
Explanation: The selection of a particular input line is controlled by a set of selected lines in a multiplexer, which helps to select a particular input from several sources.

35. If the number of n selected input lines is equal to 2^m then it requires _____ select lines.
a) 2
b) m
c) n
d) 2n
Answer: b
Explanation: If the number of n selected input lines is equal to 2^m then it requires m select lines to select one of m select lines.

36. How many select lines would be required for an 8-line-to-1-line multiplexer?
a) 2
b) 4
c) 8
d) 3
Answer: d
Explanation: 2n input lines, n control lines and 1 output line available for MUX. Here, 8 input lines mean 23 inputs. So, 3 control lines are possible. Depending on the status of the select lines, the input is selected and fed to the output.

37. A basic multiplexer principle can be demonstrated through the use of a ___________
a) Single-pole relay
b) DPDT switch
c) Rotary switch
d) Linear stepper
Answer: c
Explanation: A basic multiplexer principle can be demonstrated through the use of a rotary switch. Since its behaviour is similar to the multiplexer. There are around 10 digits out of which one is selected one at a time and fed to the output.

38. How many NOT gates are required for the construction of a 4-to-1 multiplexer?
a) 3
b) 4
c) 2
d) 5
Answer: c
Explanation: There are two NOT gates required for the construction of 4-to-1 multiplexer. x0, x1, x2 and x3 are the inputs and C1 and C0 are the select lines and M is the output.
The diagram of a 4-to-1 multiplexer is shown below:

39. In the given 4-to-1 multiplexer, if c1 = 0 and c0 = 1 then the output M is ___________

a) X0
b) X1
c) X2
d) X3
Answer: b
Explanation: The output will be X1, because c1 = 0 and c0 = 1 results into 1 which further results as X1. And rest of the AND gates gives output as 0.

40. The enable input is also known as ___________
a) Select input
b) Decoded input
c) Strobe
d) Sink
Answer: c
Explanation: The enable input is also known as strobe which is used to cascade two or more multiplexer ICs to construct a multiplexer with a larger number of inputs. Enable input activates the multiplexer to operate.

41. Which of the following is correct for multiplexer?
a) Several inputs and single output
b) Single input and several outputs
c) Single input and single output
d) Several inputs and several outputs
Answer: a
Explanation: Multiplexer has several inputs and a single output line and it is used for data selection.

42. Multiplexers work with ________________
a) Analog signal
b) Digital signal
c) Both analog and digital signal
d) None of the mentioned
Answer: c
Explanation: Multiplexers work with both analog and digital signals.

43. TDM stands for _________________
a) Time direct measurement
b) Time division multiplexing
c) Time direct multiplexing
d) Time division measurement
Answer: b
Explanation: TDM or Time division multiplexing is a type of multiplexing.

44. Which of the following is analogous to multiplexer?
a) Data selector
b) Data multiplexer
c) Data filter
d) None of the mentioned
Answer: a
Explanation: Multiplexer is similar to data selector which is used to select data from multiple input data.

45. Which of the following represent multiple input single output switch?
a) Multiplexer
b) De multiplexer
c) Both multiplexer and demultiplexer
d) None of the mentioned
Answer: a
Explanation: Multiplexer select one data line among multiple data lines and they represent multiple input single output switch.

46. Schematic symbol of multiplexer is __________________
a) Isosceles triangle
b) Isosceles trapezoid
c) Equilateral triangle
d) Rectangle
Answer: b
Explanation: Multiplexer and demultiplexer is schematically represented using isosceles trapezoid.

47. In digital multiplexer selector line is _______________
a) Analog value
b) Digital value
c) Unpredictable
d) None of the mentioned
Answer: b
Explanation: In digital multiplexer selector line is of digital value.

48. Which of the following is not a multiplexer?
a) 8-to-1 line
b) 16-to-1 line
c) 4-to-1 line
d) 1-to-4 line
Answer: d
Explanation: Multiplexer is a multiple input single output system.

49. Demultiplexer act as an encoder.
a) True
b) False
Answer: b
Explanation: Demultiplexer is basically a decoder in function.

50. Multiplexer can be used as PLD.
a) True
b) False
Answer: a
Explanation: Multiplexer can be used as PLD, by specifying the logic arrangement in the input signals, a custom logic circuit can be created.

 51. The word demultiplex means ___________
a) One into many
b) Many into one
c) Distributor
d) One into many as well as Distributor
Answer: d
Explanation: The word demultiplex means “one into many” and distributor. A demultiplexer sends a single input to multiple outputs, depending on the select lines. It is clear from the diagram:

52. Why is a demultiplexer called a data distributor?
a) The input will be distributed to one of the outputs
b) One of the inputs will be selected for the output
c) The output will be distributed to one of the inputs
d) Single input to Single Output
Answer: a
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. For one input, the demultiplexer gives several outputs. That is why it is called a data distributor. 

53. Most demultiplexers facilitate which type of conversion?
a) Decimal-to-hexadecimal
b) Single input, multiple outputs
c) AC to DC
d) Odd parity to even parity
Answer: b
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. Demultiplexer converts single input into multiple outputs.

54. In 1-to-4 demultiplexer, how many select lines are required?
a) 2
b) 3
c) 4
d) 5
Answer: a
Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select lines. Therefore, for 1:4 demultiplexer, 2 select lines are required. 

55. In a multiplexer the output depends on its ___________
a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
Answer: b
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. As the select input changes, the output of the multiplexer varies according to that input.

56. In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be ___________
a) Y0
b) Y1
c) Y2
d) Y3
Answer: d
Explanation: It can be calculated from the figure shown below:

For C0 =1 and C1 =0, Y3 will be the output as 0 and 1 are the bit combinations of 1.

57. How many select lines are required for a 1-to-8 demultiplexer?
a) 2
b) 3
c) 4
d) 5
Answer: b
Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select lines. In this case n = 3 since 23 = 8.

58. How many AND gates are required for a 1-to-8 multiplexer?
a) 2
b) 6
c) 8
d) 5
Answer: c
Explanation: The number of AND gates required will be equal to the number of outputs in a demultiplexer, which are 8.

59. The output Q4 of this 1-to-8 demultiplexer is ____________

a) Q2.(Q1)’.Q0.I
b) Q2.Q1.(Q0)’.I
c) Q2.(Q1)’.(Q0)’.I
d) Q2.(Q1).Q0.I
Answer: c
Explanation: The output Y4 = Q2.(Q1)’.(Q0)’.I. since the bit combinations of 4 are 100. 

60. Which IC is used for the implementation of 1-to-16 DEMUX?
a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
Answer: a
Explanation: IC 74154 is used for the implementation of 1-to-16 DEMUX, whose output is inverted input.

61. Why is a demultiplexer called a data distributor?
a) The input will be distributed to one of the outputs
b) One of the inputs will be selected for the output
c) The output will be distributed to one of the inputs
d) Single input gives single output
Answer: a
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. For one input, the demultiplexer gives several outputs. That is why it is called a data distributor.

62. Most demultiplexers facilitate which type of conversion?
a) Decimal-to-hexadecimal
b) Single input, multiple outputs
c) AC to DC
d) Odd parity to even parity
Answer: b
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. Demultiplexer converts single input into multiple outputs.

63. In 1-to-4 demultiplexer, how many select lines are required?
a) 2
b) 3
c) 4
d) 5
Answer: a
Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select lines. Therefore, for 1:4 demultiplexer, 2 select lines are required.

64. In a multiplexer the output depends on its ____________
a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
Answer: b
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. As the select input changes, the output of the multiplexer varies according to that input.

65. In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be ____________
a) Y0
b) Y1
c) Y2
d) Y3
Answer: d
Explanation: It can be calculated from the figure shown below:

For C0 =1 and C1 =1, Y3 will be the output as 0 and 1 are the bit combinations of 1.

66. How many select lines are required for a 1-to-8 demultiplexer?
a) 2
b) 3
c) 4
d) 5
Answer: b
Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select lines. In this case n = 3 since 23 = 8.

67. How many AND gates are required for a 1-to-8 multiplexer?
a) 2
b) 6
c) 8
d) 5
Answer: c
Explanation: The number of AND gates required will be equal to the number of outputs in a demultiplexer, which are 8.

68. Which IC is used for the implementation of 1-to-16 DEMUX?
a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
Answer: a
Explanation: IC 74154 is used for the implementation of 1-to-16 DEMUX, whose output is inverted input.

69. A decoder converts n inputs to __________ outputs.
a) n
b) n2
c) 2n
d) nn
Answer: c
Explanation: Decoder is a circuit with n input lines and 2n output lines.

70. Which of the following are building blocks of encoders?
a) NOT gate
b) OR gate
c) AND gate
d) NAND gate
Answer: b
Explanation: Encoders are made up of three OR gates.

71. Which of the following can be represented for decoder?
a) Sequential circuit
b) Combinational circuit
c) Logical circuit
d) None of the mentioned
Answer: b
Explanation: Combinational circuit in which output depends only on the state of inputs.

72. BCD to seven segment conversion is a ________________
a) Decoding process
b) Encoding process
c) Comparing process
d) None of the mentioned
Answer: a
Explanation: BCD to seven segment code conversion can be treated as a decoding process.

73. Which of the following is a decoder IC?
a) 7890
b) 8870
c) 4047
d) 4041
Answer: b
Explanation: 8870 is a DTMF decoder circuit, which decodes DTMF tune and produces corresponding output.

74. Invalid BCD can be made to valid BCD by adding with _______________
a) 0101
b) 0110
c) 0111
d) 1001
Answer: b
Explanation: Invalid BCD are numbers greater than 1001, and they can be made valid BCD by adding with 0110.

75. Decoder is constructed from ________________
a) Inverters
b) AND gates
c) Inverters and AND gates
d) None of the mentioned
Answer: c
Explanation: Decoder circuits are constructed from Inverters and AND gates.

76. Which of the following represents a number of output lines for a decoder with 4 input lines?
a) 15
b) 16
c) 17
d) 18
Answer: b
Explanation: For n input lined decoder will have 2n output lines.

10. Decoders and Encoders are doing reverse operation.
a) True
b) False
Answer: a
Explanation: Encoders encode the data to a binary number and decoders decode the original data from binary codes.